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1/39 AN1625 application note october 2003 1 introduction for small-motor applications many appliance designers favor modern three phase brushless dc motors be- cause of the high efficiency (as great as 95%) and small size for a given delivered power. designers have to handle control logic, torque and speed control, power-delivery issues and ensure safe operation in every load condition. the l6235 is a highly integrated, mixed-signal power ic that allows to easily design a complete motor control system for bldc motor. figure 1 shows the l6235 block diagram. the ic integrates six power dmos, a centralized logic circuit to decode hall effect sensors and a constant t off pwm current control technique (syn- chronous mode) plus other added features for safe operation and flexibility. figure 1. l6235 block diagram. charge pump voltage regulator hall-effect sensors decoding logic thermal protection tacho monostable ocd1 ocd ocd ocd2 10v 5v vcp vs a gate logic vboot v boot out 1 out 2 sense a vs b out 3 sense b diag en fwd/rev brake h 3 h 1 rcpulse d99in1095b tacho rcoff h 2 ocd3 one shot monostable masking time v boot ocd1 10v v boot ocd2 10v v boot ocd3 10v sense comparator + - pwm vref by vincenzo marano l6235 three phase brushless dc motor driver modern motion control applications need more flexibility that can be addressed only with specialized ics products. the l6235 is a fully integrated motor driver ic specifically developed to drive a wide range of bldc motors with hall effect sensors. this ic is a one-chip cost effective solution that includes several unique circuit design features. these features, including a universal decoding logic that allows the device to be used with most common hall effect spacing, will be described. the principal aim of this development project was to produce an easy to use, fully protected power ic. in addition several key functions as protection circuit and high speed pwm current control allow to drastically reduce the external components count to meet requirements for many different applications.
AN1625 application note 2/39 table of contents 1 introduction.................................................................................................................. ..............1 2 designing an application with l6235 ...................................................................................3 2.1 current ratings ............................................................................................................. ...........3 2.2 voltage ratings and operating range ....................................................................................3 2.3 choosing the bulk capacitor................................................................................................. ...5 2.4 layout considerations ....................................................................................................... ......5 2.5 sensing resistor ............................................................................................................ ..........7 2.6 charge pump external components .........................................................................................8 2.7 sharing the charge pump circuitry .........................................................................................9 2.8 reference voltage for pwm current control.........................................................................10 2.9 input logic pins ............................................................................................................ ..........11 2.10 diag pin................................................................................................................... ..............11 2.11 programmable off-time monostable .......................................................................................12 2.11.1 off-time selection and minimum on-time ........................................................................14 2.11.2 slow decay mode ......................................................................................................... ..14 2.12 over current detection .................................................................................................... .....16 2.13 power management ........................................................................................................... ....20 2.13.1 maximum output current vs. selectable devices..............................................................20 2.13.2 power dissipation formulae ...........................................................................................21 2.14 the decoding logic........................................................................................................ ........24 2.15 tacho output and speed loop .............................................................................................25 2.15.1 static performance - speed regulation vs. resistant torque: .......................................28 2.15.2 dynamic performance: .................................................................................................... 29 2.15.3 loop stability: ......................................................................................................... .........30 2.15.4 reference voltage ripple: ............................................................................................... .30 2.16 brake..................................................................................................................... ................31 3 application example........................................................................................................... .....32 4 appendix - evaluation boards .............................................................................................34 4.1 practispin.................................................................................................................. ............34 4.2 eval6235n ................................................................................................................... ........35 4.2.1 important notes........................................................................................................... .....36 5 references.................................................................................................................... .............39
3/39 AN1625 application note 2 designing an application with l6235 2.1 current ratings with mosfet (dmos) devices, unlike bipolar transistors, current under short circuit conditions is, at first ap- proximation, limited by the r ds(on) of the dmos themselves and could reach very high values. l6235 out pins and the two v sa and v sb pins are rated for a maximum of 2.8 a r.m.s. and 5.6 a peak (typical values). these values are meant to avoid damaging metal structures, including the metallization on the die and bond wires. in practical applications, though, maximum allowable current is less than these values, due to power dissipation limits (see power management section). the device has a built-in over current detection (ocd) that allows protection against short circuits between the outputs and between an output and ground (see over current detection section). 2.2 voltage ratings and operating range the l6235 requires a single supply voltage (v s ), for the motor supply. internal voltage regulators provide the 5v and 10 v required for the internal circuitry. the operating range for v s is 8 to 52 v. to prevent working into undesirable low supply voltage an under voltage lock out (uvlo) circuit shuts down the device when supply voltage falls below 6 v; to resume normal operating conditions, v s must then exceed 7 v. the hysteresis is pro- vided to avoid false intervention of the uvlo function during fast v s ringings. it should be noted, however, that dmos's r ds(on) is a function of the v s supply voltage. actually, when v s is less than 10v, r ds(on) is adversely affected, and this is particularly true for the high side dmos that are driven from v boot supply. this supply is obtained through a charge pump from the internal 10v supply, which will tend to reduce its output voltage when v s goes below 10v. figure 2 shows the supply voltage of the high side gate drivers (v boot - v s ) versus the supply voltage (v s ). figure 2. high side gate drivers supply voltage versus supply voltage. note that v s must be connected to both v sa and v sb because the bootstrap voltage (at v boot pin) is the same for the two h-bridges. the integrated dmos have a rated drain-source breakdown voltage of 60 v. however v s should be kept below 52 v, since in normal working conditions the dmos see a vds voltage that will exceed v s supply. in particular when a high-side dmos turns off due to a phase change (out1 in figure 3), if one of the other outputs (out2 in figure 3) is high (during the off-time all active bridges turn their high-side on) the load current starts flowing in the low-side freewheeling diode and the sense pin sees a negative spike due to a not negligible parasitic inductance of the pcb path from the pin to gnd. this spike is followed by a stable negative voltage due to the drop on r sense . the output pin sees a similar behavior, but with a slightly larger voltage due to the forward recovery time of the integrated freewheeling diode and the forward voltage drop across it. typical duration of this spike is 30 ns. at the same time, the out2 pin (in the example of figure 3) v s [v] v boot - v s [v] 6 6.4 6.8 7.2 7.6 8 8 8.5 9 9.5 10 10.5
AN1625 application note 4/39 sees a voltage above v s , due to voltage drop across the high-side (integrated) freewheeling diode, as the cur- rent reverses direction and flows into the bulk capacitor. it turns out that the highest differential voltage is ob- served between two out pins when a phase change turns a high-side off during an off-time, and this must always be kept below 60 v [2]. figure 3. currents and voltages if a phase change turns a high-side off during off-time. figure 4 shows the voltage waveforms at the out pins referring to a possible practical situation, with a peak output current of 2.8 a, v s = 52 v, r sense = 0.33 w , tj = 25 c (approximately) and a good pcb layout. below ground spike amplitude is -2.64 v for one output; the other out pin is at about 55 v. in these conditions, total differential voltage reaches almost 60 v, which is the absolute maximum rating for the dmos. keeping differ- ential voltage between two output pins within rated values is a must that can be accomplished with proper se- lection of bulk capacitor value and equivalent series resistance (esr), according to current peaks and adopting good layout practices to minimize pcb parasitic inductances (see below) [2]. figure 4. voltage at the two outputs if a phase change turns a high-side off during off-time. on-time off-time during off-time a phase change can occur pcb parasitic inductance r sense *i r sense *i+ v f(diode) bulk capacitor equivalent circuit esr esl pcb parasitic inductance v s current starts flowing in the third half bridge out1 out2 sense
5/39 AN1625 application note 2.3 choosing the bulk capacitor since the bulk capacitor, placed between v s and gnd pins, is charged and discharged during ic operation, its ac current capability must be greater than the r.m.s. value of the charge/discharge current. this current flows from the capacitor to the ic during the on-time (t on ) and from the ic (during some phase changes; from the power supply during off-time) to the capacitor during the off-time (t off ). the r.m.s. value of the current flowing into the bulk capacitor depends on peak output current, output current ripple, switching frequency, duty-cycle. it also depends on power supply characteristics. a power supply with poor high frequency performances (or long, inductive connections to the ic) will cause the bulk capacitor to be recharged slowly: the higher the current control switching frequency, the higher the current ripple in the capacitor; r.m.s. current in the capacitor, how- ever, does not exceed the r.m.s. output current. bulk capacitor value (c) and the esr determine the amount of voltage ripple on the capacitor itself and on the ic. neglecting the output current ripple and assuming that during the on-time the capacitor is not recharged by the power supply, the voltage at the end of the on-time is where i out is the output current. usually (if c>100 f) the capacitance role is much less than the esr, then supply voltage ripple can be estimated as for example, if a maximum ripple of 500 mv is allowed and i out = 2 a, the capacitor esr should be lower than note that additional ripple is due to parasitic inductances on v s pcb tracks (see voltage ratings and operating range section). actually, current sunk by v sa and v sb pins of the device is subject to higher peaks due to reverse recovery charge of internal freewheeling diodes. duration of these peaks is, tough, very short (100200 ns) and can be filtered using a small value (100200 nf), good quality ceramic capacitor, connected as close as possible to the v sa , v sb and gnd pins of the ic. bulk capacitor will be chosen with maximum operating voltage 25% greater than the maximum supply voltage, considering also power supply tolerances. for example, with a 48 v nominal power supply, with 5% tolerance, maximum voltage is 50.4 v, then operating voltage for the capacitor should be at least 63 v. 2.4 layout considerations working with devices that combine high power switches and control logic in the same ic careful attention has to be paid to the pcb layout. in extreme cases, power dmos commutation can induce noises that could cause improper operation in the logic section of the device. noise can be radiated by high dv/dt nodes or high di/dt paths, or conducted through gnd or supply connections. logic connections, especially high-impedance nodes (actually all logic inputs, see further), must be kept far from switching nodes and paths. with the l6235, in par- ticular, external components for the charge pump circuitry should be connected together through short paths, since these components are subject to voltage and current switching at relatively high frequency (600 khz). pri- mary mean in minimizing conducted noise is working on a good gnd layout (see figure 5). v s i out esr t on c -------- - + ?? ?? C i out esr esr 0.5v 2a ------------ 250m w = <
AN1625 application note 6/39 figure 5. typical application and layout suggestions. high current gnd tracks (i.e. the tracks connected to the sensing resistor) must be connected directly to the neg- ative terminal of the bulk capacitor. a good quality, high-frequency bypass capacitor is also required (typically a 100 nf200 nf ceramic would suffice), since electrolytic capacitors show a poor high frequency performance. both bulk electrolytic and high frequency bypass capacitors have to be connected with short tracks to v sa , v sb and gnd. on the l6235 gnd pins are the logic gnd, since only the quiescent current flows through them. logic gnd and power gnd should be connected together in a single point, the bulk capacitor, to keep noise in the power gnd from affecting logic gnd. specific care should be paid layouting the path from the sense pins through the sensing resistor to the negative terminal of the bulk capacitor (power ground). these tracks must be as short as possible in order to minimize parasitic inductances that can cause dangerous voltage spikes on sense and out pins (see the voltage ratings and operating range section); for the same reason the capac- itors on v sa , v sb and gnd pins should be very close to the gnd and supply pins. refer to the sensing resistors section for information on selecting the sense resistors. traces that connect to v sa , v sb , sense a , sense b , and the three out pins must be designed with adequate width, since high currents are flowing through these traces, and layer changes should be avoided. should a layer change prove necessary, multiple and large via holes have to be used. a wide gnd copper area can be used to improve power dissipation for the device. figure 6 shows two typical situations that must be avoided. an important consideration about the location of the bulk capacitor is the ability to absorb the inductive energy from the load, without allowing the supply voltage to exceed the maximum rating. the diode shown in figure 6 prevents the recirculation current from reaching the capacitors and will result in a high voltage on the ic pins that can destroy the device. having a switch or a power connection that can disconnect the capacitors from the ic, while there is still current in the motor, will also result in a high voltage transient since there is no capacitance to absorb the recirculation current. + - v s = 8 52 v v ref = 0 1v en brake f wd/rev h3 h2 h1 v ref rc off rc p ul se gnd gnd gnd gnd sense a sense b v sa v sb v boot cp out 3 out 1 out 2 d1 d2 r1 r2 r3 r4 r5 c1 c2 c3 c4 c7 c8 c5 c6 l6235 c or cu stom log ic 3 - phas e brushless dc motor + - logic supply 3.3 5 v diag tacho
7/39 AN1625 application note figure 6. two situations that must be avoided. 2.5 sensing resistor motor winding current flows through the sensing resistor, causing a voltage drop that is used, by the logic, to control the peak value of the load current. two issues must be taken into account when choosing the r sense value: n the sensing resistor dissipates energy and provides dangerous negative voltages on the sense pins during the current recirculation. for this reason the resistance of this component should be kept low. n the voltage drop across r sense is compared to the reference voltage (on vref pin) by the internal com- parator. the lower is the r sense value, the higher is the peak current error due to noise on vref pin and to the input offset of the current sense comparator: too small values of r sense must be avoided. a good compromise is calculating the sensing resistor value so that the voltage drop, corresponding to the peak current in the load (ipeak), is about 0.5 v: r sense = 0.5 v / ipeak. it should be clear that sensing resistor must absolutely be non-inductive type in order to avoid dangerous neg- ative spikes on sense pins. wire wounded resistors cannot be used here, while metallic film resistors are rec- ommended for their high peak current capability and low inductance. for the same reason the connections between the sense pins, c6, c7, v sa , v sb and gnd pins (see figure 5) must be taken as short as possible (see also the layout considerations section). the average power dissipated by the sensing resistor is: ; d is the duty-cycle of the pwm current control, i rms is the r.m.s. value of the load current. nevertheless, sensing resistor power rating should be chosen taking into account the peak value of the dissi- pated power: , where i pk is the peak value of the load current. using multiple resistors in parallel will help obtaining the required power rating with standard resistors, and re- gnd gnd gnd gnd sense a sense b v sa v sb r5 c7 c6 l6235 dont connect the logic gnd here voltage drop due to current in sense path can disturb logic gnd. dont put a diode here! recirculating current cannot flow into the bulk capacitor and causes a high voltage spike that can destroy the ic. + - v s = 8 52 v p r i rms 2 r sense d ? p r i pk 2 r sense ?
AN1625 application note 8/39 duce the inductance. r sense tolerance reflects on the peak current error: 1% resistors should be preferred. the following table shows r sense recommended values (to have 0.5v drop on it) and power ratings for typical examples of current peak values. 2.6 charge pump external components an internal oscillator, with its output at cp pin, switches from gnd to 10 v with a typical frequency of 600 khz (see figure 7). figure 7. charge pump. when the oscillator output is at ground, c5 is charged by v s through d2. when it rises to 10 v, d2 is reverse biased and the charge flows from c5 to c8 through d1, so the v boot pin, after a few cycles, reaches the max- imum voltage of v s + 10 v - v d1 - v d2 , which supplies the high-side gate drivers. with a differential voltage between v s and v boot of about 9v and the bridges switching at 50 khz, the typical current drawn by the v boot pin is 1.85ma. resistor r4 is added to reduce the maximum current in the external components and to reduce the slew rate of the rising and falling edges of the voltage at the cp pin, in order to minimize interferences with the rest of the circuit. for the same reason care must be taken in realizing the pcb layout of r4, c5, d1, d2 connections (see also the layout considerations section). recommended values for the charge pump circuitry are: i pk r sense value [ w ] r sense power rating [w] alternatives 0.5 1 0.25 1 0.5 0.5 2 x 1 w , 0.25w paralleled 1.5 0.33 0.75 3 x 1 w , 0.25w paralleled 2 0.25 1 4 x 1 w , 0.25w paralleled l6235 v s + 10 v - v d1 v s - v d1 f = 600 khz v sa v sb v bo o t cp d1 d2 r4 c8 c5 r ds (on) = 70 w 10 v 10 v 5 v r ds(on) = 70 w to high-side gate drivers 10 v f = khz char ge pump oscillator v s + 10 v - v d1 - v d2 600
9/39 AN1625 application note d1, d2 : 1n4148 r4 : 100 w (1/8 w) c5 : 10 nf 100v ceramic c8 : 220 nf 35v ceramic due to the high charge pump frequency, fast diodes are required. connecting the cold side of the bulk capacitor (c8) to v s instead of gnd the average current in the external diodes during operation is less than 10 ma (with r4 = 100 w ); at startup (when v s is provided to the ic) is less than 200 ma while the reverse voltage is about 10 v in all conditions. 1n4148 diodes withstand about 200 ma dc (1 a peak), and the maximum reverse voltage is 75 v, so they should fit for the majority of applications. 2.7 sharing the charge pump circuitry if more than one device is used in the application, it's possible to use the charge pump from one l6235 to supply the v boot pins of several ics. the unused cp pins on the slaved devices are left unconnected, as shown in figure 8. a 100 nf capacitor (c8) should be connected to the v boot pin of each device. supply voltage pins (v s ) of the devices sharing the charge pump must be connected together. the higher the number of devices sharing the same charge pump, the lower will be the differential voltage avail- able for gate drive (v boot - v s ), causing a higher r ds(on) for the high side dmos, so higher dissipating power. in this case it's recommended to omit the resistor on the cp pin, obtaining a higher current capability of the charge pump circuitry. better performance can also be obtained using a 33 nf capacitor for c5 and using schottky diodes (for example bat47). sharing the same charge pump circuitry for more than 34 devices is not recommended, since it will reduce the v boot voltage increasing the high-side mos on-resistance and thus power dissipation. figure 8. sharing the charge pump circuitry. l6235 v sa v sb v boo t cp c18 = 100 nf to high-side gate drivers l6235 v sa v sb v bo o t c8 = 100nf to high-side gate drivers to ot her devices cp d1 = bat47 d2 = bat47 c5 = 33nf
AN1625 application note 10/39 2.8 reference voltage for pwm current control the device has an analog input, vref, connected to the internal sense comparator, to control the peak value of the motor current through the integrated pwm circuitry. a fixed reference voltage can be easily obtained through a resistive divider from an available 5 v voltage rail (maybe the one supplying the c or the rest of the applica- tion) and gnd. a very simple way to obtain a variable voltage without using a dac is to low-pass filter a pwm output of a c (see figure 9). figure 9. obtaining a variable voltage through a pwm output of a c. assuming that the pwm output swings from 0 to 5v, the resulting average voltage will be where d c is the duty-cycle of the pwm output of the c. assuming that the c output impedance is lower than 1k w, with r lp = 56k w , r div = 15k w , c lp = 10nf and a c pwm switching from 0 to 5v at 100khz, the low pass filter time constant is about 0.12 ms and the remaining ripple on the v ref voltage will be about 20 mv. using higher values for r lp , r div and c lp will reduce the ripple, but the reference voltage will take more time to vary after changing the duty-cycle of the c pwm, and too high values of r lp will also increase the impedance of the v ref net at low frequencies, causing a poor noise immunity. as sensing resistor value is typically kept small, a small noise on v ref input pins might cause a considerable error in the output current. it's then recommended to decouple this pin with a ceramic capacitor of some tens of nf, placed very close to vref and gnd pins. note that vref pin cannot be left unconnected, while, if connected to gnd, zero current is not guaranteed due to voltage offset in the sense comparator. the best way to cut down (ic) power consumption and clear the load current is pulling down the en pin. with very small reference voltage, pwm integrated circuitry can loose control of the current due to the minimum allowed duration of t on (see the programmable off-time monostable section). r lp c lp v ref gnd pwm output of a c r div v ref 5v d m c r div r lp r div + ---------------------------------------- - =
11/39 AN1625 application note 2.9 input logic pins h1, h2, h3, fwd/rev, brake, enable, are cmos/ttl compatible logic input pins. the input comparator has been realized with hysteresis to ensure the required noise immunity. typical values for turn-on and turn-off thresholds are v th(on) = 1.8 v and v th(off) = 1.3 v. pins are esd protected (see figure 10) (2kv human-body electro-static discharge), and can be directly connected to the logic outputs of a c; a series resistor is generally not recommended, as it could help inducted noise to disturb the inputs. all logic pins enforce a specific behavior and can- not be left unconnected. if connected to the diag pin, en pin must be driven through a series resistor of 2.2 k w min- imum (for 5 v logic), to allow the voltage at the pin to be pulled below the turn-off threshold (see below). figure 10. logic input pins. 2.10 diag pin diag pin is an open-drain output pulled to gnd in case of overcurrent or over temperature conditions. connect- ing this pin to en will allow the internal open drain to disable all the power dmos of the l6235, provided that the en pin is driven through a resistor (see input logic pins). a capacitor (c1 in figure 5 and figure 11) connected between en and diag pins and gnd is also recommend- ed, to reduce the r.m.s. value of the output current when overcurrent conditions persist (see over current pro- tection section). figure 11. diag pin. 5 v h1 , h2 h3 , fw d/ rev , brake , enable esd protection di ag en c1 r1 c or logic output
AN1625 application note 12/39 2.11 programmable off-time monostable the l6235 includes a constant off time pwm current controller. the current control circuit senses the bridge current by sensing the voltage drop across an external sense resistor connected between the source of the three lower power mos transistors and ground, as shown in figure 12. as the current in the motor increases the voltage across the sense resistor increases proportionally. when the voltage drop across the sense resistor becomes greater than the voltage at the reference input pin vref the sense comparator triggers the monostable switching the bridge off. the power mos remain off for the time set by the monostable and the mo- tor current recirculates around the upper half of the bridge in slow decay mode as described in the next section. when the monostable times out, the bridge will again turn on. since the internal dead time, used to prevent cross conduction in the bridge, delays the turn on of the power mos, the effective off time t off is the sum of the monostable time plus the dead time. figure 13 shows the typical operating waveforms of the output current, the voltage drop across the sensing re- sistor, the pin rc voltage and the status of the bridge. more details regarding the synchronous rectification and the output stage configuration are included in the next section. immediately after the power mos turn on, a high peak current flows through the sense resistor due to the re- verse recovery of the freewheeling diodes. the l6235 provides a 1s blanking time t blank that inhibits the comparator output so that the current spike cannot prematurely retrigger the monostable. figure 12. pwm current controller simplified schematic drivers + dead time s q r drivers + dead time drivers + dead time out 3 out 2 sense b sense a r sense d02in1380 rcoff r off c off vref out 1 + + - - 1 m s 5ma blanker sense comparator monostable set 2.5v 5v from the low-side gate drivers blanking time monostable vs b vs vs a to gate logic (0) (1)
13/39 AN1625 application note figure 13. output current regulation waveforms figure 14 shows the magnitude of the off time t off versus c off and r off values. it can be approximately calculated from the equations: t rcfall = 0.6 r off c off t off = t rcfall + t dt = 0.6 r off c off + t dt where r off and c off are the external component values and t dt is the internally generated dead time with: 20k w r off 100k w 0.47nf c off 100nf t dt = 1s (typical value) therefore: t off(min) = 6.6s t off(max) = 6ms these values allow a sufficient range of t off to implement the drive circuit for most motors. the capacitor value chosen for c off also affects the rise time t rcrise of the voltage at the pin rc off . the rise time t rcrise will only be an issue if the capacitor is not completely charged before the next time the monostable is triggered. therefore, the on time t on , which depends by motors and supply parameters, has to be bigger than t rcrise for allowing a good current regulation by the pwm stage. furthermore, the on time t on can not be smaller than the minimum on time t on(min) . off bc dd a t on t off bc on 2.5v 0 slow decay slow decay 1 m s t blank t rcrise t rcrise synchronous rectification 1 m s t blank 5v v rc v sense v ref i out v ref r sense d02in1351 t off 1 m s t dt 1 m s t dt t rcfall t rcfall
AN1625 application note 14/39 t rcrise = 600 c off 2.11.1 off-time selection and minimum on-time figure 14 also shows the lower limit for the on time t on for having a good pwm current regulation capacity. it has to be said that t on is always bigger than t on(min) because the device imposes this condition, but it can be smaller than t rcrise - t dt . in this last case the device continues to work but the off time t off is not more con- stant. so, small c off value gives more flexibility for the applications (allows smaller on time and, therefore, higher switching frequency), but, the smaller is the value for c off , the more influential will be the noises on the circuit performance. figure 14. off-time selection and minimum on-time. 2.11.2 slow decay mode figure 15 shows the operation of the bridge in the slow decay mode during the off time. at any time only two legs of the three-phase bridge are active, therefore only the two active legs of the bridge are shown in the figure and the third leg will be off. at the start of the off time, the lower power mos is switched off and the current t on t on min () > 1.5 m s (typ. value) = t on t rcrise t dt C > ? ? ? 0.1 1 10 100 1 10 100 1 . 10 3 1 . 10 4 coff [nf] to f f [u s] 0.1 1 10 100 1 10 100 coff [nf] to n ( m in ) [ u s] r = 20 k w r = 47 k w r = 100 k w
15/39 AN1625 application note recirculates around the upper half of the bridge. since the voltage across the coil is low, the current decays slow- ly. after the dead time the upper power mos is operated in the synchronous rectification mode reducing the impedance of the freewheeling diode and the related conducting losses. when the monostable times out, upper mos that was operating the synchronous mode turns off and the lower power mos is turned on again after some delay set by the dead time to prevent cross conduction. figure 15. slow decay mode output stage configurations in some conditions (short off-time, very low regulated current, high motor winding l / r) the system may need an on-time shorter than 1.5 s. in these cases the pwm current controller can loose the regulation. figure 16 shows the operation of the circuit in this condition. when the current first reaches the threshold, both the high-side are turned on for a fixed time and the current decays. during the following on-time current increases above the threshold, but the bridge cannot be turned off until the minimum on-time expires. since current increases more in each on-time than it decays during the off-time, it keeps growing during each cycle, with steady state asymptotic value set by duty-cycle and load dc resistance: the resulting peak current will be i pk = v s d / r load , where d = t on / (t on +t off ) is the duty-cycle and r load is the load resistance. figure 16. minimum on-time can cause the pwm controller to loose the regulation. a) on time b) 1 m s dead time c) synchronous rectification d) 1 m s dead time d01in1336 needed t on is less than 1.5 s minimum t on is about 1.5 s v ref / r sense
AN1625 application note 16/39 2.12 over current detection to implement an over current (i.e. short circuit) protection, a dedicated over current detection (ocd) circuitry (see figure 17 for a simplified schematic) senses the current in each high side. power dmos are actually made up with thousands of individual identical cells, each carrying a fraction of the total current flowing. the current sensing element, connected in parallel to the power dmos, is made only with few such cells, having a 1:n ratio compared to the power dmos. the total drain current is split between the output and the sense element ac- cording to the cell ratio. sensed current is, then, a small fraction of the output current and will not contribute significantly to power dissipation. figure 17. over current detection simplified circuitry. this sensed current is compared to an internally generated reference to detect an over current condition. an internal open drain mosfet turns on when the sum of the currents in the bridges 1 and 2 or the current in the bridge 3 reaches the threshold (5.6a typical value); the open drain is available at the diag pin for diagnostic purposes or to ensure an over current protection, connecting en and diag together and using an rc network (see figure 17). + over temperature i ref i ref i 1 +i 2 / n i 1 / n high side dmos power sense 1 cell power sense 1 cell power sense 1 cell power dmos n cells power dmos n cells power dmos n cells high side dmos high side dmos out 1 out 2 vs a out 3 vs b i 1 i 2 i 3 i 2 / n i 3 / n ocd comparator to gate logic internal open-drain r ds(on) 40 w typ. c en r en diag en v dd m c or logic d02in1381
17/39 AN1625 application note figure 18. over current operation after a short circuit between an out pin and gnd. en and diag pins are connected together. figure 18 shows the device operating in overcurrent condition (short to ground). when an over current is de- tected the internal open drain mosfet pulls the en pin to gnd switching off all 6 power dmos of the device and allowing the current to decay. under a persistent over current condition, like a short to ground or a short between two output pins, the external rc network on the en pin (see figure 17) reduces the r.m.s. value of the output current by imposing a fixed disable-time after each over current occurrence. the values of r en and c en are selected to ensure proper operation of the device under a short circuit condition. when the current flowing through the high side dmos reaches the ocd threshold (5.6 a typ.), after an internal propagation delay (t ocd(on) ) the open drain starts discharging c en . when the en pin voltage falls below the turn-off threshold (v th(off) ) all the power dmos turn off after the internal propagation delay (t d(off)en ). the current begins to decay as it circulates through the freewheeling diodes. since the dmos are off, there is no current flowing through them and no current to sense so the ocd circuit, after a short delay (t ocd(off) ), switches the internal open drain device off, and r en can charge c en . when the voltage at en pin reaches the turn-on threshold (v th(on) ), after the t d(on)en delay, the dmos turn on and the current restarts. even if the maximum output cur- rent can be very high, the external rc network provides a disable time (t disable ) to ensure a safe r.m.s. value (see figure 18). the maximum value reached by the current depends on its slew-rate, so on the short circuit nature and supply voltage, and on the total intervention delay (t delay ). it can be noticed that after the first current peak, the max- imum value reached by the output current becomes lower, because the capacitor on en and diag pins is dis- charged starting from a lower voltage, resulting in a shorter t delay . the following approximate relations estimate the disable time and the first ocd intervention delay after the short circuit (worst case). the time the device remains disabled is: v en(low) is the minimum voltage reached by the en pin, and can be estimated with the relation: en = diag output current v th(off) t d(off)en i s over t ocd(on) t disable t ocd(off) t delay t en(fall) t en(rise) v en(low) e n = diag output current t disable v th(on) t d(on)en t disable t ocd off () t en rise () t don () en ++ = t en rise () r en c en v dd v en low () C v dd v th on () C ------------------------------------------- - ?? ?? ln =
AN1625 application note 18/39 the total intervention time is where t ocd(off) , t ocd(on) , t d(on)en , t d(off)en , and r opdr are device intrinsic parameters, v dd is the pull-up voltage applied to r en . the external rc network, c en in particular, must be chosen obtaining a reasonable fast ocd intervention (short t delay ) and a safe disable time (long t disable ). figure 19 shows both t disable and t delay as a function of c en : at least 100s for t disable are recommended, keeping the delay time below 12s at the same time. the internal open drain can also be turned on if the device experiences an over temperature (ovt) condition. the ovt will cause the device to shut down when the die temperature exceeds the ovt threshold (t j >165 c typ.). since the ovt is also connected directly to the gate drive circuit (see figure 1), all the power dmos will shut down, even if en pin voltage is still over v th(off) . when the junction temperature falls below the ovt turn-off threshold (150 c typ.), the open drain turns off, c en is recharged up to v th(on) and then the powerdmos are turned on back. v en low () v th off () e t doff () t ocd off () + r opdr c en ------------------------------------------------- - ?? ?? = t delay t ocd on () t en fall () t doff () en ++ = t en fall () r opdr c en v dd v th off () ------------------------ - ?? ?? ln =
19/39 AN1625 application note figure 19. typical disable and delay time as a function of c en , for several values of r en . 1 10 100 0.1 1 10 t delay [s] c en [n f ] 1 10 100 1 10 100 1 . 10 3 c en [n f ] t disable [s] r en = 220 k w r en = 100 k w r en = 47 k w r en = 33 k w r en = 10 k w
AN1625 application note 20/39 2.13 power management even when operating at current levels well below the maximum ratings of the device, the operating junction tem- perature must be kept below 125 c. figure 20 shows the ic dissipated power versus the r.m.s. load current, in 4 different driving sequences, assum- ing the supply voltage is 24v. figure 20. ic dissipated power versus output current. 2.13.1 maximum output current vs. selectable devices figure 21 reports a performance comparison between l6229 (std. power) and l6235 (high power) for different packages, with the following assumptions: - supply voltage: 24 v; switching frequency: 30 khz. - t amb = 25 c, t j = 125 c. - maximum r ds(on) (taking into account process spread) has been considered, @ 125 c. - maximum quiescent current i q (taking into account process spread) has been considered. - pcb is a fr4 with a dissipating copper surface on the top side of 6 cm 2 (with a thickness of 35 m) for so and powerdip packages (d, n suffixes). - pcb is a fr4 with a dissipating copper surface on the top side of 6 cm 2 (with a thickness of 35 m), 16 via holes and a ground layer for the powerso package (pd suffix). - for each device (on the x axis) y axis reports the maximum output current. no pwm f sw = 30 khz (slow decay) test conditions: supply voltage = 24 v 0 0.5 1 1.5 2 2.5 3 0 2 4 6 8 10 p i out [a] d [w] i out i 1 i 3 i 2 i out i out
21/39 AN1625 application note figure 21. maximum output current vs. selectable devices. 2.13.2 power dissipation formulae figure 22 to figure 25 are screenshots of a spreadsheet that helps calculating power dissipation in specified conditions (application and motor data), and estimates the resulting junction temperature for a given package and copper area available on the pcb [3]. the model considers power dissipation during the on-time and the off-time, taking into account the selected de- cay, rise and fall time (when a phase change occurs), the switching losses and the quiescent current power dis- sipation. l 6 2 2 9 d l 6 2 2 9 n l 6 2 2 9 p d l 6 2 3 5 d l 6 2 3 5 n l 6 2 3 5 p d 0.50 0.70 0.90 1.10 1.30 1.50 1.70 1.90 2.10 2.30 load current [a]
AN1625 application note 22/39 figure 22. current in the three phases and the signal of one of the hall effect sensors. figure 23. input data. t = 1 / f el 1 / f hall = t ( f hall = f el = n * f mec h ) i 1 i 2 i 3 i pk i d d i d d i d d i i pk i i pk i t rise t fall t rise t fall t rise t fall hall input data maximum drain-source on resistance ron = 5.60e-01 [ w ] average value between high-side and low-side maximum diode voltage vd = 1.20e+00 [v] quiescent current iq = 5.50e-03 [a] maximum bemf voltage vb = 1.00e+01 [v] motor inductance lm = 8.00e-04 [h] motor resistance rm = 2.10e+00 [ w ] polar couples n = 1 - supply voltage vs = 2.40e+01 [v] peak current ipk = 1.50e+00 [a] off-time toff = 8.00e-06 [s] sensing resistance rs = 3.30e-01 [ w ] motor speed sp = 1.00e+04 [rpm] device input values motor input values application input values
23/39 AN1625 application note figure 24. power dissipation formulae and results. result powerdmos commutation time tcom = 9.60e-08 [s] vs / (250v/ m s) electrical frequency fel = 1.67e+02 [hz] n*sp/60 rise time trise = 5.65e-5 [s] fall time tfall = 5.13e-05 [s] duty cycle d = 6.08e-01 - vb+i(2*ron+rm))/(vs -i*rs) switching frequency fsw = 4.90e+04 [hz] (1-d) / toff current ripple d i = 3.19e-01 [a] 2.1*((2ron+rm)*ipk+vb)*toff/lm period t = 6.00e-03 [s] 1 / fel load time tload = 5.66e-03 [s] t-6trise average current during load time i = 1.34e+00 [a] r.m.s. current during load time irms = 1.34e+00 [a] rise time dissipating power prise = 1.58e-02 [w] fall time dissipating power pfall = 3.00e-02 [w] load time diss. power pload = 1.91e-00 [w] (2ron irms 2 tload) / t commutation dissipating pw pcom = 2.86e-01 [w] (2vs i tcom tload fsw) / t quiescent dissipating pw pq = 1.32e-01 [w] vs iq total dissipat- ing power p = 2.37e+00 [w] pq + pcom + pload + pfall + prise ipk rm 2 2ipk ron ipk rs vs + C C C () vs ------------------------------------------------------------------------------------------------------------------- lm rm rs 2ron ++ --------------------------------------------- - ln C vs 2 vd C ipk rm ipk + rs vs 2 vd () C + () ----------------------------------------------------------------------------------------------- - lm rm rs + () ---------------------------- ln C ipk d i 2 ----- C ipk ipk i d C () i 2 d 3 ------- - + 2ron ipk 2 trise 3 -------------- - ?? ?? 2 t --- 2 t --- 2 vd tfall vs C 2vd + () rm rs + () -------------------------------------- lm ipk rm ipk rs vs 2 vd C + + () 1 t C fall lm ---------------- rm rs + () exp C rm rs + () 2 -------------------------------------------------------------------------------- - +
AN1625 application note 24/39 figure 25. thermal data inputs and results 2.14 the decoding logic the l6235 integrated decoding logic provides the correct sequence on the three outputs for motors with both 60 and 120 spaced hall effect sensors signals. the sensors' outputs are directly connected to the h1, h2, h3 inputs of the device. the table below reports the output configurations for all possible hall effect input signals. hall 120 123a-456a- hall 60 12-3b45 -6b h 1 hhlhl lh l h 2 lhhhhll l h 3 l l l hhhh l out 1 vs high z gnd gnd gnd high z vs vs out 2 high z vs vs vs high z gnd gnd gnd out 3 gnd gnd high z high z vs vs high z high z phasing 1->3 2->3 2->1 2->1 3->1 3->2 1->2 1->2 input dat a package powerso36 copper area 5.0 110 sq. cm copper area is on same side of the device ground layer yes ambient temperature 50 -25 100 oc results thermal resistance junction to ambient 20.81 oc / w thermal resistance junction to pins / slug 1.00 oc / w estimated junction temperature 99.35 oc estimated pins / slug temperature 96.98 oc
25/39 AN1625 application note 2.15 tacho output and speed loop h1 input is internally connected to a monostable that provides, through an open drain mosfet, a fixed width pulse on the tacho output (see figure 26). through this output realizing a speed loop is very easy and inexpensive. providing an external pull-up resistor on this open drain output, the resulting waveform at the pin will be a square-wave whose frequency is proportional to the motor rotation speed, with a fixed on-time (t pulse ) set by an external rc network connected at the rc pulse pin. figure 26. tacho monostable. tacho monostable is identical to rcoff monostable, and the fixed pulse time is defined by: figure 27. tacho pulses selection. rc pulse h1 tacho tacho monostable to the decoding logic +5v gnd hall effect sensor 1 from the motor t pulse t pulse 0.6r pulse c pulse @ 1 10 100 10 100 1 . 10 3 1 . 10 4 cpul [nf] tpulse [ m s] r pul = 100k w r pul = 47k w r pul = 20k w
AN1625 application note 26/39 also the duty cycle of this signal, so its average value is proportional to the motor rotation speed. simply inte- grating the square-wave a voltage proportional to the motor speed will be available to realize a speed loop, as in figure 28: r pulse and c pulse define the fixed on-time (t pulse ) of the tacho output, integrated and compared to a voltage proportional to the desired speed (v speed ) by the op-amp; the output of the op-amp represents the speed error signal. providing this signal to the vref input of the l6235, which sets the current in the motor wind- ings, the speed error will act on the motor modifying its torque, in order to maintain the speed at a constant value. r1 and r2 set the maximum current in the motor by limiting the voltage at the v ref pin. figure 28. tacho output allows easy implementation of a speed loop. defining k t motor torque constant [nm/a] d dynamic friction torque [nms/rad] j motor + load inertia moment [kgm2] t r load resistant torque [nm] t m = j/d mechanical time constant [s] n number of polar couples w m motor rotation speed [rad/s] f tacho = n w m / 2 p tacho output frequency [hz] t i = c fb r fb2 integrator time constant [s] g op-amp = r fb2 /r fb1 g w-v =v pullup n t pulse / 2 p [vs/rad] g 1 =r 2 / r sense (r 1 +r 2 )[1/ w ] and neglecting the current ripple due to pwm control, the expression of the control loop transfer function (see figure 29) is: rc pulse tacho v ref l6235 c pulse r pulse r pullup c fb r fb2 r 1 r 2 v speed t pulse v pullup r f b1 h 1 h 2 h 3 out 1 out 2 out 3 bldc motor v ref v op-amp v t acho r sense sense a sense b
27/39 AN1625 application note figure 29. control loop block diagram. can be noticed that since the motor is current controlled, the electrical time constant of the motor (l/r) does not appear in any transfer function. with the following values, module and phase of g loop are shown in figure 30. k t = 9.8 mnm/a d = 3.34 nms/rad j = 6.5 kgm 2 t r = 4 mnm t m = j/d = 1.95 s (mechanical pole at 0.08 hz) n = 2 w m = 2618 rad/s (25000 r.p.m.) f tacho = n w m / 2 p = 833 hz v pullup = 5v t pulse = 1 ms r fb1 = 100 k w r fb2 = 1 m w c = 33 nf r 1 = 5.6 k w r 2 = 1.8 k w r sense = 0.33 w g loop s () g op amp C g w v C g 1 k t C d1s t i + () 1s t m + () ---------------------------------------------------------------------- = 2 1 2 r r r + sense r 1 1 2 fb fb r r 2 p n t v pulse pullup m [rad/s] [v] [v] [v] [a] i s t + 1 1 t k m s t d + 1 / 1 t [nm] t r [nm] + _ + _ + + g op-amp g 1 g w - v v speed [v] g motor w
AN1625 application note 28/39 figure 30. g loop module and phase. the relation between the speed reference voltage (v speed ), the load resistant torque (t b ) and the motor speed ( w m ) is given by the expression: for a given speed, the speed reference voltage to apply is: designing the speed loop, care must be taken choosing the values of r pullup , r fb1 , r fb2 , c fb , r 1 and r 2 obtaining a good compromise between static performance, dynamic performance, stability and torque ripple: 2.15.1 static performance - speed regulation vs. resistant torque: the relation between v speed , t b and w m shows that for a fixed speed reference, the load torque (t b ) affects the speed. to minimize the resistant torque effect the term (d + g w -v g 1 k t g op-amp ) must be kept as high as possible. figure 31 shows how the speed changes with the load torque, and percentage regulation error. due to the op-amp output voltage saturation, beyond a certain load torque value the system cannot produce further torque, then the motor speed drastically decreases. 1 . 10 3 0.01 0.1 1 10 100 50 25 0 25 50 f [hz] |gloop| [db] fc 0 1 . 10 3 0.01 0.1 1 10 100 135 90 45 f [ hz ] phase of gloop [ ] fc 180 w m v speed 1 g op amp C 1s t i + ------------------------ - + ?? ?? g 1 k t t b C d1s t m () g w v C g 1 k t g op amp C 1s t i + ------------------------ - ++ ----------------------------------------------------------------------------------------------------------- = v speed w m dg w v C g 1 k t g op amp C + () t b + 1g op amp C + () g 1 k t ------------------------------------------------------------------------------------------------------------ =
29/39 AN1625 application note figure 31. regulated speed variations versus mechanical load. 2.15.2 dynamic performance: the loop bandwidth is the frequency range in which the loop gain is greater than 1 (0 db). in the example it's about 2.5 hz. it expresses how fast will the loop regulate the speed after load changes. the transfer function between the resistant torque and the motor speed is , while between speed reference voltage and speed we have: figure 32 and figure 33 show how the speed changes after applying a 1mn resistant torque step and a 1v speed voltage step, respectively 0.005 0.01 0.015 0.02 0.025 0.03 1.5 . 10 4 2 . 10 4 2.5 . 10 4 3 . 10 4 resistant torque (tb) [nm] regulated speed vref=4.17 v vref=4.67 v vref=3.67 v 0 0.005 0.01 0.015 0.02 0.025 0.03 10 8 6 4 2 0 resistant torque (tb) [nm] % speed regulation error vref=4.17 v 3.5 . 10 4 w m s () t b s () ---------------- 1s t 1 + () C d -------------------------- 1s t m + () 1s t i + () 1 d --- - g w v C g op amp C g 1 k t + ------------------------------------------------------------------------------------------------------------------------------- ------- = w m s () v speed s () -------------------------- 1 g op amp C 1s t i + ------------------------ - + ?? ?? g 1 k t d1s t m + () g w v C g 1 k t g op amp C 1s t i + ------------------------ - + ----------------------------------------------------------------------------------------------------------- =
AN1625 application note 30/39 figure 32. speed response to a 1mnm resistant torque step figure 33. speed response to a 1v speed voltage step. 2.15.3 loop stability: the phase margin is defined as 180 minus the phase of gloop at the cut frequency (where gloop=1). it should be at least 45 to guarantee the stability. in the example it's about 65. 2.15.4 reference voltage ripple: due to the tacho waveform integration, the reference voltage provided to the l6235 v ref input is a triangular wave (see figure 27). the ripple can be calculated through the approximate relation: , where dc is the duty-cycle of the square wave at the tacho output: since this reference voltage is the torque control voltage, the ripple should be kept as low as possible, accordingly to others main parameters. in the example the ripple is about 60 mv. 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 100 80 60 40 20 0 t [s] speed variation [r. p.m.] 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 1600 3200 4800 6400 8000 t [s] speed variation [r.p.m. ] d v ref speedref 1 dc C () r fb1 f tacho c fb ------------------------------------------------------ r 2 r 1 r 2 + -------------------- = dc nt pulse w m 2 p ---------------------------------- - =
31/39 AN1625 application note the limits of this system depend on the fact that the speed information is obtained by an analog integration of the tacho output. this operation introduces a low frequency pole in the gl oop function, and a ripple in the ref- erence voltage. the introduced pole, in conjunction with the very low frequency mechanical pole of the motor, strongly affects loop stability, system bandwidth and static speed regulation error: to preserve stability a dc loop gain (g loop (0)) diminution may be needed. at the same time, decreasing the reference voltage ripple requires to reduce the frequency of the integrator pole, cutting the bandwidth and reducing the phase margin. a full digital approach to convert the tacho frequency in a voltage can give further improvement in static and dynamic speed regulation: a microcontroller can measure the frequency of the tacho output and provide the ref- erence voltage to the l6235 through a d/a converter or a low-pass filtered (see reference voltage section) pwm output (whose frequency can be much higher than the hall effect signals frequency, resulting in a strongly reduced vref ripple). another possibility is using a pll to generate a voltage proportional to the speed (or used directly, taking a fre- quency input as the command). 2.16 brake in general, motor braking can be achieved making a short circuit across the windings: the bemf forces a cur- rent, proportional to the braking torque, that flows in the opposite direction than in normal running mode. for high bemf and inertia moment the current may reach very high values: a power resistor is often used to reduce the maximum braking current and dissipate the motor energy. l6235 brake pin can be used to quickly stop the motor while it is running: providing a low logic level to this pin all the high-side dmos switch on, making a short-circuit across the motor windings. a power resistor is not used: while the motor is braking, both thermal and over current protections still work, avoiding bemf to cause a current exceeding the device's maximum ratings. connecting en and diag pins together and using a rc network (see over current detection section) a disable time between each over current event can be set, reducing the maximum r.m.s. value of the current. figure 34 and figure 35 show what happens if the current exceeds the ocd threshold while the motor is brak- ing: as soon as the current in one of the three motor phases reaches the ocd threshold (5.6 a typ.) the open drain mosfet internally connected to the diag pin discharges the external capacity; the en pin voltage falls to gnd and all the bridges of the device are disabled for a time that depends on the rc network values. during this disable time the current forced by the bemf decreases, and so the braking torque; when the current be- comes zero (because the motor inductances have been fully discharged), if the bemf is less than the supply voltage there is no braking effect (since the freewheeling diodes cannot be turned on) until the disable time ex- pires and all the high side powerdmos turn on again
AN1625 application note 32/39 figure 34. overcurrent during motor braking. figure 35. overcurrent during motor braking. 3 application example application data rotation speed: 10000 rpm (f el =167hz) winding peak current: 1.5 a maximum ripple: 350ma maximum bemf at 10000rpm: 10 v on-time braking overcurrent C disable time i 1 en = diag i 2 i 3 brake command
33/39 AN1625 application note motor data winding resistance (2 phases): 2 w winding inductance (2 phases): 800 m h supply voltage: 24 v +/- 5% polar couples: 1 referring to approximated formulae in figure 24, it's possible to calculate the duty cycle (d), the switching fre- quency (f sw ), the current ripple ( d i). with a 8 s off-time, we will have: d @ 61%, f sw @ 49 khz, d i @ 320 ma. the on-time is t on = d / f sw @ 12.5 s, which is far from the minimum allowed (1.5 s). the bulk capacitor needs to withstand at least 24 v + 5% + 25% @ 32 v. a 50 v capacitor will be used. allowing a voltage ripple of 200 mv, the capacitor esr should be lower than 200 mv / 1a = 200 m w ; the ac current capability should be about 1.5 a (worst case). providing a reference voltage of 0.5 v, 0.33 w sensing resistor are needed. the resistors power rating is about pr @ irms 2 r sense d @ 0.37 w. three 1 w / 0.25 w - 1% resistors in parallel are used. the charge pump uses recommended components (1n4148 diodes, ceramic capacitors and a 100 w resistor to reduce emi). r = 24 k w , c = 470 pf are connected to the rc pins, obtaining t off @ 7.8 m s. on the en pin a 5.6 nf has been placed, and the pin is driven by the m c through a 100 k w resistor. with these values, in case of short circuit between two out pins or an out pin and gnd, the powerdmos turns off after about 1 m s, and t disable @ 240 m s. figure 36. application example. referring to figure 23, figure 24, figure 25, the dissipating power is about 2.37 w. if the ambient temperature is lower than 50 c, with 5 cm 2 of copper area on the pcb, a ground layer and a powerso36 package, the estimated junction temperature is about 97 c. + - v s = 24 v v ref = 0.5 v en h1 brake cw/ccw h3 h2 v ref rc pulse rc off gnd gnd gnd gnd sense a sense b v sa v sb v boot cp out 3 out 1 out 2 1n4148 1n4148 100 k w 24 k w 1% 100 w 0.25w 5.6 nf ceramic 47nf ceramic 470 pf ceramic 100nf 50v ceramic 220nf 35v ceramic 10nf 50v ceramic 100f 50v esr<200m w l6235 c or cu stom log ic 3 - phase brushless dc motor + - 3 x 1 w , 0.25 w, 1% 2 k w 0.25 w 1% 18 k w 0.25 w 1% logic supply 5 v tacho diag
AN1625 application note 34/39 4 appendix - evaluation boards 4.1 practispin practispin is an evaluation and demonstration system that can be used with the powerspin family (l62xx) of devices. a graphical user interface (gui) (see figure 37) program runs on an ibm-pc under windows and com- municates with a common st7 based interface board (see figure 38) through the rs232 serial port. the st7 interface board connects to a device specific evaluation board (target board) via a standard 34 pin ribbon cable interface. depending on the target device the practispin can drive a stepper motor, 1 or 2 dc motors or a brushless dc (bldc) motor, operating significant parameters such as speed, current, voltage, direction, accel- eration and deceleration rates from a user friendly graphic interface, and programming a sequence of movements. the software also allows evaluating the power dissipated by the selected device and, for a given package and dissipating copper area on the pcb, estimates the device's junction temperature. figure 37. practispin pc software
35/39 AN1625 application note figure 38. practispin st7 evaluation board 4.2 eval6235n an evaluation board has been produced to help the evaluation of the device in powerdip package. it imple- ments a typical application with several added components. figure 40 shows the electrical schematic of the board; in the table below the part list is reported. the evaluation board provides external connectors for the supply voltage, an external 5 v reference for the logic inputs, three outputs for the motor and a 34-pin connector to control the main functions of the board through an external m c board. running the evaluation board in stand-alone mode, instead, four switches (s1) allow enabling the device, set- ting the direction of the rotation, braking the motor, choosing to run in torque or speed mode. r17 and r22 set cn1, cn2 2-poles connector jp1, jp2 2-pin jumper cn3 3-poles connector r1 700 w 0.6w resistor cn4 34-poles connector r2,r3,r4,r7,r8,r9 10k w resistor c1 220nf/100v ceramic or polyester capacitor r5 100 w resistor c2 220nf/100v ceramic or polyester capacitor r15,r6 1k w resistor c3 100f/63v capacitor r11,r10 100k w trimmer c4 10nf/100v ceramic capacitor r12,r13,r14 1 w 1% resistor c5 10f/16v capacitor r16 1m w resistor c6 33nf capacitor r17 20k w resistor c7 1nf capacitor r18 4.7k w resistor c8 820pf capacitor r19 5.6k w resistor c9 10nf capacitor r20 2.2k w resistor c10 220nf capacitor r21 1.8k w resistor c11 68nf capacitor r22 5k w trimmer c12 100nf capacitor s1 quad switch d1, d2 1n4148 diode u1 l6235n d3 bzx79c5v1 5.1v zener diode u2 lm358
AN1625 application note 36/39 the reference voltage provided to the vref pin of the l6235 (in torque mode) or to the error amplifier, u2 (in speed mode); r20, c11 make up a low-pass filters to provide an external reference voltage by a pwm output of a m c (see also the reference voltage section). r10, c8 are used to set the off-time and r11, c9 set the duration of the tacho output pulses. the 5v voltage for logic inputs and for the reference voltage is obtained from r1, d3. for supply voltages great- er than 20v, r1 must be replaced with a higher value resistor. the jumper jp1 and jp2 allow disconnecting the internal zener diode network, in case the 5v voltage is provided through pin 11 of cn5 (for example an external c board can provide 5 v to the evaluation board). also cn2 connector can be used to provide an external 5 v voltage to the board. cn2, or pin 1 of cn5, can also be used to provide a 5 v voltage to external circuits. in this case only a small current can be drawn form the board, depending on the supply voltage and r1 value. figure 41, figure 42, figure 43 show the component placement and the two layers layout of the l6235n evaluation board. a large gnd area has been used, to guarantee minimal noise and good power dissipation for the device. figure 39. eval6235n. 4.2.1 important notes jp1 : close for use with practispin st7 board jp2 : close for use with practispin st7 board c6 : recommended change to 5.6 nf for safe overcurrent protection r2 : recommended change to 100 k for safe overcurrent protection r6 : recommended change to 100 k (and remove r2) if en pin is driven from the cn4 connector (for example with practispin st7 board) for safe overcurrent protection r22 : set the maximum current obtainable through practispin (see practispin documentation) r1 : recommended change to adequate value (depending on supply voltage) to obtain 5v across d3 s1 : move first switch in trq position for use with practispin st7 board jp1 jp2 c6 r6 r2 r22 r1 1 st switch of s1
37/39 AN1625 application note figure 40. l6235n evaluation board electrical schematic. +5v +5v vccref +5v vccref pul lup +5v tp tp tp pullup pullup pullup +5v pullup p2.2 p2.1 p2.6 p2.7 p2.5 hall con p2.4 tina0 p2.0 cw cw cw int3 int2 ocmpa1 p4.2 p3.1 adc_ref a0in6 p7.6 l6235 n brake en trq rev speed fw cn4 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 cn5 1 2 3 4 5 c10 r16 cn1 1 2 cn2 1 2 c5 d2 r5 c2 c9 r11 c8 r10 r2 r4 r3 d3 r17 r20 c3 r6 r9 c1 cn3 1 2 3 jp1 r18 c4 d1 r8 r7 c12 u2a lm358 + - 3 2 1 8 4 jp2 r1 r19 r15 r21 u2b lm358 + - 5 6 7 8 4 s1 9 11 16 8 1 15 10 14 2 13 3 12 4 5 6 7 c6 c11 r22 r12 u1 l6235 out1 5 sense1 3 out3 16 rcoff 4 out2 21 tacho 8 h1 1 diag 2 rcpulse 9 vref 13 h2 23 fwr/rew 11 sense2 10 brake 14 h3 24 enable 12 gnd 6 gnd 7 vboot 15 vsb 17 gnd 18 gnd 19 vsa 20 vcp 22 c7 r14 r13 sense rc/inh h3 h1 enable h2 frw/rev brake h1 h2 h3 diag h3 frw/rew h1 diag enable h2 vref h1 vref brake
AN1625 application note 38/39 figure 41. l6235 evaluation board component placement. figure 42. l6235 evaluation board top layer layout. power gnd signal gnd bulk capacitor
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com 39/39 AN1625 application note figure 43. l6235 evaluation board bottom layer layout. 5 references 1 d. arrigo, a. genova, t. hopkins, v. marano, a. novelli, "a new fully integrated stepper motor driver ic", proceedings of pcim 2001, september 2001, intertech communication. 2 t. hopkins, "controlling voltage transients in full bridge driver applications" (an280). 3 p. casati and c. cognetti, "a new high power ic surface mount package family" (an668). sense path

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